As packaging density in semiconductor devices continues to increase, three-dimensional (3D) wafer-to-wafer stacking has become a viable solution for accommodating an increased number of devices within a specific “footprint” (surface area) of a given package. 3D wafer stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, as well as greater integration through system-on-chip (SoC) solutions. In addition, the 3D technology may provide other functionality to the chip.
One factor in achieving manufacturable and cost-effective 3D wafer configurations relates to providing reliable and repeatable electrical bonding between wafers within the stack. An exemplary approach for providing wafer-to-wafer bonding is defined as “direct bonding”, which can be thought of as using conventional wafer fabrication techniques (including wafer thinning, photolithography masking, via etching and interconnect metallization) to create bond pad areas (“posts”) on each wafer. The wafers are then disposed one on top of another such that the posts face each other. Presuming the posts are properly aligned, the wafers are bonded together, forming both physical attachment and electrical signal path connection between the wafers.
One critical parameter in the direct bond interface (DBI) process is the flatness that can be obtained on an exposed top surface of the wafer within which the metal posts are formed. After the metal is deposited in the vias formed in the wafer, a planarization process is used to even out the upper surface of the wafer and expose a planar array of post surfaces. In most cases, a chemical mechanical polishing (CMP) operation is used to perform this planarization. It is well known, however, that “dishing” (removal of metal below the final surface of the structure) occurs during CMP and is directly proportional to the diameter of the post. That is, the larger the diameter of the post, the wider and deeper the dishing that may result. Obviously, if the dishing is too severe, electrical connection between mating posts is compromised.
While decreasing the diameter of the posts is a reasonable solution to overcome the dishing problem, the use of small diameter posts impacts the ability of conventional wafer bonding tools to align one wafer with another when forming the vertical wafer stack. In other words, the overlay accuracy of the bonding tool ultimately determines the reliability and repeatability of the DBI process.